1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the invention concerns a method of polishing for planarization when manufacturing a semiconductor device.
2. Description of the Related Art
Nowadays, in the process of executing multi-layer wiring, a lot of use has been made of a step wherein after forming a wiring pattern on a relevant substrate, an insulation film is formed and the surface of the resulting mass is planarized using a chemical-mechanical polishing process (hereinafter, referred to as “the CMP”).
The outline of the multi-layer wiring process will now be explained using FIG. 1A. First, on a wiring pattern 102 on which a substrate 101 is formed, there is formed a SiO2 film 103 that serves as a protection/adhesion layer for the wiring pattern 102. On the resultant SiO2 film 103, there is coated and embedded an Spin on glass (SOG) film 104. Thereafter, CMP is performed with respect to the SOG film 104 under the conditions that the polishing selectivity can be set between the SOG film 104 and the SiO2 film 103, thereby performing planarization.
Also, in another form of example, as illustrated in FIG. 2A, on a substrate having a wiring pattern 102 formed thereon, a SiO2 film 103 that serves as a protection/adhesion layer for the wiring pattern 102 is formed, and CMP is performed with respect to the resultant SiO2 film 103, thereby performing planarization.
It has hitherto been proposed that for CMP with respect to these insulation films 103, 104 there be used slurry using silica or cerium oxide as the polishing particles, further a slurry prepared by adding thereto anionic or nonionic surfactant.
However, in the earlier techniques, as described below, the problems that are to be improved remained unsolved.
As illustrated in FIGS. 1B and 1C, in a case where, using, for example, a slurry containing cerium oxide 105 and anionic surfactant 108, performing CMP by relatively moving a polishing pad 107 and the substrate 101, since the polishing selectivity of the SOG film 104 to the SiO2 film 103 is low, the SiO2 film 103 is eliminated, which tends to scratch the wiring pattern.
Especially, as the wiring becomes micronized, the thickness of the SiO2 film 103 tends to be made thinner and, therefore, it was fairly difficult to polish the SOG film 104 so that the SiO2 film 103 that had been made thin was not eliminated.
Also, as illustrated in FIG. 2B, in a case where there is used the slurry of the earlier technology, containing the cerium oxide 105 and anionic surfactant 108, polishing particles were easy to leave behind on the surface of the insulation film.